Design and Implementation of Low Power VLSI Circuit using VHDL

Authors:P. RAHUL REDDY, D. PRASAD

0945-0951

Design of Low Power, Area Efficient and High Speed 3-Bit Decoder

Authors:CHAITRA B B

0952-0956

VLSI Implementation of a High Speed Single Precision Floating Point Multiplier using Verilog

Authors:GUNTUKA SWETHA, V. SANDEEP KUMAR

0957-0961

FPGA Implementation of High Speed 8-Bit Vedic Multiplier using Barrel Shifter

Authors:GURRAM SRAVANTHI, B.KISHORE BABU

0962-0965

Design and Estimation of Delay, Power and Area for Parallel Prefix Adders

Authors:NERADI GANGADHAR, P.ASHOK KUMAR

0966-0971

Enhanced Area Efficient Architecture for 128 BIT Modified CSLA

Authors:PAYYAVULA SWATHI, B. KISHORE BABU

0972-0975

A Novel Fault Detection and Correction Technique for Memory Applications

Authors:RAJKUMAR JARPULA, Y.SINGARAIAH

0976-0981

High Speed Convolution and Deconvolution Algorithm (Based on Ancient Indian Vedic Mathematics)

Authors:K. LEELA SANTHISHI, B. MUNILAKSHMI

0982-0985